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Wally on Genesys 2 FPGA board?
enhancement
New feature or request
#1086
opened Nov 12, 2024 by
matsbror
Unexplained extra bit in FMA data path
enhancement
New feature or request
#970
opened Sep 29, 2024 by
davidharrishmc
Concurrent HPTW access fault with IFU bus fetch
enhancement
New feature or request
#845
opened Jun 19, 2024 by
rosethompson
Possible optimization: tlbcamline.sv
enhancement
New feature or request
#844
opened Jun 19, 2024 by
rosethompson
Setup continuous FPGA regression test and performance validation
enhancement
New feature or request
#780
opened May 6, 2024 by
rosethompson
More tests in nightly regression
enhancement
New feature or request
#779
opened May 6, 2024 by
davidharrishmc
Remove flush from EBU critical path
enhancement
New feature or request
#771
opened May 2, 2024 by
davidharrishmc
Testfloat on Verilator not progressing
enhancement
New feature or request
#707
opened Apr 4, 2024 by
davidharrishmc
RAS return after return bug
enhancement
New feature or request
#610
opened Feb 1, 2024 by
rosethompson
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