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30 Open 183 Closed
30 Open 183 Closed
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Issues list

Reference to non-existing debug_mode_o signal in user manual Component:Doc For issues in the Documentation (e.g. for User Manual, README.md files) Type:Bug For bugs in any content (RTL, Documentation, etc.)
#984 opened Sep 30, 2024 by Silabs-ArjanB
Use access fault exceptions for non naturally aligned LR/SC and AMOs Component:RTL For issues in the RTL (e.g. for files in the rtl directory) Type:Bug For bugs in any content (RTL, Documentation, etc.)
#983 opened Sep 12, 2024 by Silabs-ArjanB
1
User Manual block diagram does not illustrate the eXtension Interface Component:Doc For issues in the Documentation (e.g. for User Manual, README.md files)
#980 opened Feb 16, 2024 by MikeOpenHWGroup
@davideschiavone
Set misa.B when all of Zba, Zbb, Zbs are supported Component:RTL For issues in the RTL (e.g. for files in the rtl directory) PARAM:B_EXT Issue depends on the B_EXT parameter Type:Enhancement For feature requests and enhancements
#979 opened Jan 4, 2024 by Silabs-ArjanB
[XIF] Coprocessor XIF Issue response not sampled by ID-EX pipeline registers Component:RTL For issues in the RTL (e.g. for files in the rtl directory) Type:Bug For bugs in any content (RTL, Documentation, etc.)
#941 opened Sep 7, 2023 by StMiky
@Silabs-ArjanB
3
[X2] AMO dont set rvfi_mem_rmask Component:Other Non-RTL, non-documentation (e.g. bhv, sva) Type:Bug For bugs in any content (RTL, Documentation, etc.)
#912 opened Aug 18, 2023 by silabs-krdosvik
[XIF] Assertion a_sleep_inactive_signals fails when X_EXT=1 Component:RTL For issues in the RTL (e.g. for files in the rtl directory) Type:Bug For bugs in any content (RTL, Documentation, etc.)
#867 opened Jun 2, 2023 by silabs-oysteink
[XIF] Issue_req.id not updating and missing commit_valid Component:RTL For issues in the RTL (e.g. for files in the rtl directory) Type:Bug For bugs in any content (RTL, Documentation, etc.)
#814 opened Mar 24, 2023 by davidmallasen
2
Track corev-binutils-gdb issues Component:Other Non-RTL, non-documentation (e.g. bhv, sva) Type:Task For any task except bug fixes
#809 opened Mar 20, 2023 by Silabs-ArjanB
[XIF] Redundant mem_result when using CORE-V-XIF Component:RTL For issues in the RTL (e.g. for files in the rtl directory) Type:Bug For bugs in any content (RTL, Documentation, etc.)
#800 opened Mar 8, 2023 by davidmallasen
1
14
[XIF] Need wdata/rdata alignment if using OBI wider than 32 bit for doing standard RISC-V byte, halfword, word transfers
#672 opened Sep 27, 2022 by Silabs-ArjanB
[XIF] LSU may send mpu_status to WB too early Component:RTL For issues in the RTL (e.g. for files in the rtl directory) Type:Bug For bugs in any content (RTL, Documentation, etc.)
#653 opened Aug 25, 2022 by silabs-oysteink
2
[XIF] Forwarding of data from WB with X_EXT=1 is not working. Component:RTL For issues in the RTL (e.g. for files in the rtl directory) Type:Bug For bugs in any content (RTL, Documentation, etc.)
#652 opened Aug 25, 2022 by silabs-oysteink
[XIF] Exceptions on X-interface does not cause the core to take an exception Component:RTL For issues in the RTL (e.g. for files in the rtl directory) Type:Bug For bugs in any content (RTL, Documentation, etc.)
#651 opened Aug 25, 2022 by silabs-oysteink
[XIF] The controller FSM's XIF commit tracking signals sometimes fail to be reset Component:RTL For issues in the RTL (e.g. for files in the rtl directory) Type:Bug For bugs in any content (RTL, Documentation, etc.)
#610 opened Jul 6, 2022 by michael-platzer
1
1
[X2] Avoid JALR related timing path Component:RTL For issues in the RTL (e.g. for files in the rtl directory)
#523 opened Apr 28, 2022 by Silabs-ArjanB
[X2] Avoid CLIC related timing path Component:RTL For issues in the RTL (e.g. for files in the rtl directory)
#522 opened Apr 28, 2022 by Silabs-ArjanB
[XIF] Interrupts cleared too late Component:RTL For issues in the RTL (e.g. for files in the rtl directory) Type:Bug For bugs in any content (RTL, Documentation, etc.)
#507 opened Apr 8, 2022 by Silabs-ArjanB
4
[DOC] Impact of fence, fence.i on table jumps and CLIC vectored mode
#488 opened Mar 25, 2022 by Silabs-ArjanB
[XIF] Add X_DUALREAD, X_DUALRWRITE parameters, dbg signal on result interface, change width of dualread to 3 bits good first issue
#479 opened Mar 22, 2022 by Silabs-ArjanB
[DOC] Document when fence instructions are needed
#478 opened Mar 21, 2022 by Silabs-ArjanB
[XIF] Finalize be vs. size Component:RTL For issues in the RTL (e.g. for files in the rtl directory) Type:Task For any task except bug fixes
#464 opened Feb 28, 2022 by Silabs-ArjanB
[XIF] Scoreboard Component:RTL For issues in the RTL (e.g. for files in the rtl directory) Type:Task For any task except bug fixes
#463 opened Feb 28, 2022 by Silabs-ArjanB
[XIF] Too many instructions can execute after interrupt becomes pending and enabled Component:RTL For issues in the RTL (e.g. for files in the rtl directory) Type:Bug For bugs in any content (RTL, Documentation, etc.)
#325 opened Nov 22, 2021 by Silabs-ArjanB
7
[XIF] Implement even/odd write in register file Component:RTL For issues in the RTL (e.g. for files in the rtl directory) good first issue Type:Task For any task except bug fixes
#298 opened Oct 27, 2021 by Silabs-ArjanB
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