SERV 1.2.1

A new release of the award-winning SERV, the world's smallest RISC-V CPU is here. Biggest change this time is support for the new RISCOF compliance framework that replaces the old riscv-arch-tests, but there are also a couple of fixes, improved documentation and support for the ICE-V Wireless FPGA board.

SERV 1.2.0

New features

The 1.2.0 version of the award-winning SERV, the world's smallest RISC-V CPU focuses on features rather than size reduction as has previously been the case. Most notably, two major ISA extensions are now supported but there are also a number of other new features as can be seen below.

Servant

The SERV reference SoC, Servant, has gained support for the following new FPGA boards:

• EBAZ4205
• Chameleion96
• Nexys2 500
• Nexys2 1200
• Alinx AX309

With this, the total number of officially supported boards is 26

M extension

As part of Google Summer of Code 2021, Zeeshan Rafique implemented support for the M ISA extension. This was done through an extension interface that allows the MDU (multiplication and division unit) to reside outside of the core and potentially be shared by several SERV cores in the same SoC or integrated into other RISC-V cores for maximum reusability. Zeeshan's report about the project to add the M extension can be read here

C extension

As part of the Linux Foundation Mentorship program Spring 2022, Abdul Wadood has implemented support for the C ISA extension. The C extension has been the most requested feature of SERV. Since SERV is so small, the memory typically dominates the area and the C extension has the potential to allow for smaller memories and by extension a smaller system. Abdul's report about the project to add the C extension can be read here

ViDBo support

Support for the Virtual Development Board protocol has been added, making it possible to interact with a simulation of an FPGA board running a SERV SoC, just as it would be a real board. This allows anyone to build software for SERV and try it in simulation without access to a real board.

OpenLANE support

Thanks to the FOSSi OpenLANE toolchain, SERV can be implemented as an ASIC with the SkyWater 130nm library. It has also been fabbed as part of the Subservient SoC but at the time of this release the chips have not yet returned from the fab. Thanks to the combination of a FuseSoC, a FOSSi ASIC toolchain and publicly available CI resources however, a GDS file of SERV is now created on every commit to the repository, making the ASIC process about as agile as it can get.

Documentation

Documentation continue to improve with more gate-level schematics, written documentation, source code comments and timing diagrams towards the goal of becoming the best documented RISC-V CPU.

Bug fixes

• A bug that caused immediates to occasionally get the wrong sign (depending on which instruction was executed prior to the failing one) was found and fixed.
• Model/QuestaSim compatibility has been restored after accidentally being broken after the 1.1.0 release.

Compliance tests

Version 2.7.4 of the RISC-V compliance test suite is now supported over the older 1.0 release. A Github CI action has also been created to test the compliance test suites with all valid combinations of ISA extensions for improved test coverage.

SERV 1.1.0

New features

Many of the new features of SERV 1.1.0 are described in the latest SERV video SERV : RISC-V for a fistful of gates but below here you will find a complete list of major changes from SERV 1.0

Serving

A new helper component called the Serving SoClet has been created to make it easy to integrate SERV into FPGA designs. Serving consisting of SERV+register file+data/instruction memory and exposes a wishbone bus for connecting peripherals.

Servant

The SERV reference SoC, Servant, has gained support for the following new FPGA boards:

• Xilinx zcu106
• Radiona ULX3S 85k
• Icezum Alhambra II
• Gnarly Grey Upduino2
• Saanlima pipistrello
• Avnet LX9 Microboard
• GsD OrangeCrab
• Lattice iCEstick
• Terasic DE0 Nano
• Xilinx ac701
• Muselab iCEsugar
• Digilent CMOD-A7-35t
• Arrow SoCkit
• Arrow DECA Max10
• Terasic DE10 Nano
• Nandland Go

With this, the total number of officially supported boards is 21

Zephyr

Supports Zephyr 2.4. With this, instructions have been vastly simplified and all SERV-specific support code is contained separately within the SERV repository.

Other

• Compatible with Xilinx ISE
• Compatible with RISC-V compliance tests v1.0
• New RESET_STRATEGY parameter to control the amount of reset to apply to the core
• Github actions for CI

Optimizations

• Approximately 20% smaller than SERV 1.0

Documentation

Almost all internal modules have been documented with a functional description and gate-accurate block diagrams. Important internal and external sequences have also been documented with timing diagrams. Source code is also heavily commented.